A particular architectural concept that has allowed for more flexibility in computer design and also in computer programming has been the concept of microinstructions. Initially, a microinstruction was thought of as merely a set of control bits employed within a macroinstruction format. Such control bits were, for example, employed to provide a corrective measure during the execution of a multiplying instruction or shift instruction and the like. Gradually, as the microprogramming concept enlarged, the macroinstruction specified the particular routine to be performed, such as the addition of two operands. The execution of the macroinstruction was then accomplished through a sequence of executions of microinstructions, each of which specified the particular gates to be set thereby. Since a plurality of macroinstructions could be implemented by a finite set of microinstructions, it was then apparent that these same microinstructions could be stored in a separate storage to be addressed in a particular sequence upon the execution of different macroinstructions. It was further recognized that various sequences of microinstructions could be formulated to carry out the particular operations and separately stored in any memory. Thus, a great variety of sequences of microinstructions could be created to carry out a great variety of routines.
The concept of microinstructions or microprograms, then, became one of providing sub-instructional sets which were masked or hidden from the programmer, thereby simplifying the writing of particular programs by minimizing the number of individual specific steps that had to be called for by the programmer.
Microprogramming may thus be broadly viewed as a technique for designing and implementing the control function of a digital computer system as sequences of control signals that are organized on a word basis and stored in a fixed or dynamically changeable control memory. Detailed examples of some known approaches to the design of microprogrammed digital computers can be found in U.S. Pat. No. 3,886,523, Ferguson et al., issued May 27, 1975, U.S. Pat. No. 4,155,120, Keefer and Kim, issued May 15, 1979, U.S. Pat. No. 4,181,935, Feeser and Gerhold, issued Jan. 1, 1980 and U.S. Pat. No. 4,038,643, Kim, issued July 26, 1977; in the book by S. S. Husson, "Microprogramming: Principles and Practices", Prentice-Hall, Inc. (1970); in the book "Foundations of Microprogramming", Argrausala, et al., Academic Press, Inc., 1976; in the article "Microprogramming-Another Look at Internal Computer Control", M. J. Flynn, I.E.E.E. Proc., Vol. 63, No. 11, November 1975, pp. 1554-1567; and in the article "Microprogramming: A Tutorial and Survey of Recent Developments", I.E.E.E. Transactions on Computers, Vol. C-29, No. 1, January 1980.
The contents and teachings of the above references are to be regarded as incorporated herein.
As will be apparent from the referenced Husson book, a prior art microprogram control memory may typically comprise a selectively addressable control memory having microinstruction control words stored at selectable addressable locations thereof. In order to provide for branching, each control word may typically include, in addition to the microinstruction bits, special next address bits and condition select bits which are applied to branching logic along with system condition signals to determine the address of the next microinstruction.
From a speed viewpoint, a critical operation of a microprogrammed data processor resides in the selecting and fetching of a next microinstruction from a plurality of possible next microinstructions. In typical prior art systems, the worst-case time period required for selecting and fetching the next microinstruction is the cumulative time required for (1) selecting the processor condition bits in response to the condition select bits accompanying the current microinstruction, then (2) combining these selected condition bits with the next address bits to form the address of the next microinstruction, and finally (3) using this next microinstruction address to read out the next microinstruction from the microprogram control memory. Typically, this selecting and fetching of the next microinstruction is overlapped with the execution of the current microinstruction in order to reduce their effect on overall processing speed. However, the selection and fetching time still remains as a significant limitation on overall processing speed.